Semiconductor devices are often packaged on die pads with lead frames. The lead frames provide leads that allow for electrical connection from the device package to other components of a device or system. Electrical connections are made from leads on the lead frame to conductive pads on the semiconductor device through bond wires. There are a number of rules that affect the routing of the bond wires. One rule is that two bond wires cannot cross. Another rule is that bond wires must be less than a predetermined maximum length. Typically, the maximum length for a bond wire is about 200-300 mils. These rules may present problems when a semiconductor device package is designed by one manufacturer and uses semiconductor device components from two or more different manufacturers. An example of such a situation may arise, e.g., in the context of a battery controller circuit.
A typical battery pack used in portable electronic apparatuses includes a plurality of bare cells, a protective circuit module (PCM) in which a protective circuit for controlling the charge and discharge of the bare cells is formed, and a terminal line for electrically connecting the bare cells and the protective circuit to each other. The bare cells, the PCM, and the terminal line can be accommodated in a predetermined case.
The charge management system and battery protection IC offer extensive battery over-voltage and over-current protection, battery pre-conditioning and one percent charger voltage accuracy. They are placed in a small thermally enhanced lead frame package which may be a small surface mount device (SMD).
Conventional technologies to further reduce the size of battery protection integrated circuit (IC) are challenged by several technical difficulties and limitations. Conventional battery protection IC typically includes a power control IC and integrated dual common-drain metal oxide semiconductor field effect transistors (MOSFETs), which are packed in a lead frame package with a small foot print of a size as small as 2×5 mm. A composite or co-packaged device includes a power control IC stacked on top of integrated dual common-drain MOSFETs or overlapping two discrete MOSFETs with a single die pad may be utilized for attaching the MOSFETs of all configurations. FIG. 1A is a top view of a co-packaged device assembly 100 of the Prior Art.
As shown in FIG. 1A, dual common-drain MOSFETs 106 and 108, fabricated as a single piece of semiconductor chip, may be of the same source and gate size and attached onto a die pad 101 positioned on a lead frame 104. The die pad 101 may be separate from the lead frame 104 or may be an integral flat portion of the lead frame. The dual common drain MOSFETs 106, 108 may be fabricated as a single semiconductor chip that comprises a single dual common drain MOSFET die. The source and gate layout of the dual MOSFETs may be symmetric along the centerline of the MOSFETs. A power control IC 102 is stacked on top of the dual MOSFETs 106 and 108. In a preferred embodiment, the power control IC 102 may be non-conductively stacked on top of the dual MOSFETs 106 and 108. The substrate for the power control IC 102 is electrically isolated from the top of the dual MOSFETs 106 and 108. Input pads for the voltage monitor VM and supply voltage VDD of the power control IC 102 may be electrically connected to the VM and VCC leads of the lead frame 104 through bond wires 112 and 113 respectively. In the example illustrated in FIG. 1, input pad DP (a test pin for delay time shortening) may be electrically connected to a corresponding DP lead on the lead frame 104 through a bond wire 109. Output CO and DO pads of the power control IC 102 are electrically connected to gate pads G1 and G2 of MOSFETs 106 and 108 through bond wires 114 and 115 respectively. The VSS pad of power control IC 102 is electrically connected to VSS lead through a bond wire 116. Source pads 51 of the MOSFET 106 and source pads S2 of the MOSFET 108 may be electrically connected to OUTM lead and VSS and VSS1 leads through multiple bond wires 110 and 122 respectively.
However, as part of the application requirement for a battery PCM, the manufacturer of the PCM often utilizes a particular layout control IC 102 and MOSFETS 106, 108 that is incompatible with the pinout for a standard control IC 102 provided by the IC manufacturer. For example in the situation illustrated in FIG. 1A, in the pinout for the control IC 102 the DP pad is located between the VM and OUTM pads. As a result of this pinout and the layout of the IC 102 and MOSFETs 106, 108 on the die pad 101 and lead frame 104, the bond wires 109 and 112 would cross each other as shown in FIG. 1A. Such a crossing of bond wires is prohibited by standard wire bonding rules since it presents the risk of a short circuit. This rule applies even if the one wire is routed underneath the other so that the two wires avoid touching each other.
A straightforward solution for the bonding wire crossing problem as described above in FIG. 1A is shown in FIG. 1B. Pads on IC 102 are re-layout such that DP and VM pad positions are swapped. As shown in FIG. 1B, bond wires 109 and 112 do not cross each other. However, this solution requires a redesign of the control IC 102. Although seemingly straightforward, such a solution typically involves tremendous amount of effort, e.g., feasibility, cost, development time, may be needed to re-layout the pinout for the pads on the IC 102. This adds to the cost of the assembly 100. Also, the IC manufacturer may not be willing to re-design their IC.
Another solution for the bonding wire crossing problem is described in U.S. application Ser. No. 11/944,313, in which a different control IC 202 is used as shown in FIGS. 2A and 2B. FIG. 2A is a top view, and FIG. 2B is a cross-sectional view taken along a section B-B of the semiconductor package of FIG. 2A. In this example, the control IC 202 may be a standard IC that does not include DP pads. As shown in FIG. 2A, dual common-drain MOSFETs 206 and 208 may be of the same source and gate size and attached onto a die pad 200. The source and gate layout of the dual MOSFETs may be symmetric along the centerline of the MOSFETs. The power control IC 202 is stacked on top of the dual MOSFETs 206 and 208 and overlaps both portions of the source areas of MOSFETs 206 and 208 but not the gate areas. An insulating adhesive layer 203, such as an electrically non-conductive epoxy layer is used to attach the power control IC 202 to MOSFETs 206 and 208. The common drain pad of the MOSFETs 206 and 208 may be attached to the die pad 200 through an electrically conductive bonding agent 201. Input pads for the voltage monitor VM and supply voltage VCC of the power control IC 202 may be electrically connected to the VM and VCC leads of the package through bond wires 212 and 213 respectively. Output CO and DO pads of the power control IC 202 are electrically connected to gate pads G1 and G2 of MOSFETs 206 and 208 through bond wires 214 and 215 respectively. The VSS pad of power control IC 202 is electrically connected to the top source pad S2 of the MOSFET 208 through a bond wire 216. Source pads 51 of the MOSFET 206 and top source pads S2 of the MOSFET 208 may be electrically connected to fused OUTM leads 218 and fused VSS and VSS1 lead 220 through multiple bond wires 210 and 222 respectively.
Although this solution avoids the wire crossing problem, the die pad 200 has a different pinout than the die pad 104 of FIGS. 1A-1B. Often the manufacturer of the package assembly 100 has a specific pinout requirement for the die pad which cannot be changed without substantial re-engineering of the entire package assembly. Also a customer may not be willing to buy a part with a non-standard pinout. Furthermore, the manufacturer of the package assembly 100 may require the use specific control IC 102 and the DP output. In such a case, a substitution of the type shown in FIGS. 2A-2B may not be possible.
It would be desirable to develop a package which would use the same or smaller package for integrated dual common-drain MOSFETs while avoiding problems with bond wire crossing. It would be further desirable to produce such a package with a thinner package thickness. It would also be desirable to implement a solution that does not require changing the control IC pinout or the die pad layout. It would be further desirable if the solution could be implemented by the manufacturer of the MOSFETs.